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ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 1 ssr014-0b 08/13/2002 document title 8mb syncburst pipelined sram revision history revision no history draft date remark 0a initial draft september 24,2001 0b 1. move the ft pin for user-configurable flow august 13,2002 throught or pipelineed operation, that pin can be nc or connected to v cc for pipelined operation. refer to pin configuration. 2. revise the power supply charaetoristics at page 12 3. resive the t kq of 250 mhz from 2.5ns to 3ns. 4. move the 100 mhz speed grade. the attached datasheets are provided by icsi. integrated circuit solution inc reserve the right to change the specifications a nd products. icsi will answer to your questions about device. if you have any questions, please contact the icsi offices.
ic61s25632t/d ic61s25636t/d ic61s51218t/d 2 integrated circuit solution inc. ssr014-0b 08/13/2002 icsi reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated circuit solution inc. features ? pipeline mode operation ? single/dual cycl deselect ? user-selectable output drive strength with xq mode ? internal self-timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? pentium? or linear burst sequence control using mode input ? common data inputs and data outputs ? jedec 100-pin tqfp and 119-pin pbga package ? single +3.3v, +10%, ?5% core power supply ? power-down snooze mode ? 2.5v or 3.3v i/o supply ? snooze mode for reduced-power standby ? t version (three chip selects) ? d version (two chip selects) description icsi's 8mb syncburst pipelined srams integrate a 512k x 18, 256k x 32, or 256k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. applicationsapplications applicationsapplications applications the icsi syncburst pipelined sram family employs high-speed ,low-power cmos designs that are fabricated using an advanced cmos process to provide level 2 cache applications supporting pentium and powerpc microprocessors originally, the device now finds applica- tion ranging from dsp main store to networking chip set support. 256k x 32, 256k x 36, 512k x 18 8mb s/dcd syncburst pipelined srams controls all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst ad- dresses can be generated internally and controlled by the adv (burst address advance) input pin. the mode pin is used to select the burst sequence order, linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating. scd and dcd pipelined reads the device is a scd (single cycle deselect) and dcd(dual cycle deselect) pipelined synchronous sram. dcd srams pipeline disable commands to the same degree as read commands. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turning off their outputs immediately after the deselect command has been captured in the input registers. dcd rams hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. the user may configure this sram for either mode of operation using the scd mode input on bump 4l. byte write and global write write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to four bytes wide as controlled by the write control inputs.separate byte enables allow individual bytes to be written. byte write operation is performed by using byte write enable ( bwe ).input combined with one or more individualbyte write signals ( bwx ). in addition, global write ( gw) is available for writing all bytes at one time, regardless of the byte write controls. iol/ioh drive strength options the xq pin allows selection between high drive strength (xq low) for multi-drop bus applications and normal drive strength (xq floating or high) point-to-point applications. see the output driver characteristics chart for details. snooze mode low power (snooze mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during snooze mode. fast access time symbol -250 -200 -166 -133 units pipeline t kq 3 3.1 3.5 4 ns 3-1-1-1 t kc 4 5 6 7.5 ns i cc 1 390 360 330 300 ma
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 3 ssr014-0b 08/13/2002 block diagram 18/19 binary counter gw clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 16/17 18/19 address register d clk q dqd byte write registers d clk q dqc byte write registers d clk q dqb byte write registers d clk q dqa byte write registers d clk q enable register d clk q enable delay register d clk q bwe bwd (t, d)ce (t) ce 2 (t, d) ce2 bwa bwb 256kx32; 256kx36; 512kx18 memory array 32, 36, or 18 input registers clk output registers clk oe 4 oe dqa - dqd 32, 36, or 18 32, 36, or 18 an-a0 (x32/x36) (x32/x36/x18) (x32/x36) (x32/x36/x18) bwa
ic61s25632t/d ic61s25636t/d ic61s51218t/d 4 integrated circuit solution inc. ssr014-0b 08/13/2002 nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd scd vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc sa sa ce ce2 bwd bwc bwb bwa sa vcc gnd clk gw bwe oe adsc adsp adv sa sa nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 vcc xq gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc nc a10 sa sa sa sa sa sa 46 47 48 49 50 nc pin configuration 119-pin pbga (top view) 100-pin tqfp (d version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq sa ce2 sa nc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 nc sa nc nc sa sa sa gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode sa nc adsp adsc vcc xq ce oe adv gw vcc clk scd bwe a1 a0 vcc sa nc sa sa sa gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd nc sa nc sa sa sa nc dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 nc sa nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 note:b a ll r5 connecting to v cc is acceptable note:pin 14 connecting to v cc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 5 ssr014-0b 08/13/2002 nc dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd scd vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 nc sa sa ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv sa sa nc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc xq gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc sa sa sa sa sa sa sa sa 46 47 48 49 50 pin configuration 100-pin tqfp (t version) 256k x 32 pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce ,ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable note:pin 14 connecting to vcc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d 6 integrated circuit solution inc. ssr014-0b 08/13/2002 pin configuration 119-pin pbga (top view) 100-pin tqfp (d version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o a b c d e f g h j k l m n p r t u vccq nc nc dqc1 dqc2 vccq dqc5 dqc7 vccq dqd1 dqd4 vccq dqd6 dqd8 nc nc vccq sa ce2 sa dqpc dqc3 dqc4 dqc6 dqc8 vcc dqd2 dqd3 dqd5 dqd7 dqpd sa nc nc sa sa sa gnd gnd gnd bwc gnd nc gnd bwd gnd gnd gnd mode sa nc adsp adsc vcc xq ce oe adv gw vcc clk scd bwe a1 a0 vcc sa nc sa sa sa gnd gnd gnd bwb gnd nc gnd bwa gnd gnd gnd nc sa nc sa sa sa dqpb dqb6 dqb5 dqb4 dqb2 vcc dqa7 dqa5 dqa4 dqa3 dqpa sa nc nc vccq nc nc dqb8 dqb7 vccq dqb3 dqb1 vccq dqa8 dqa6 vccq dqa2 dqa1 nc zz vccq 1 2 3 4 5 6 7 dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd scd vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa sa sa ce ce2 bwd bwc bwb bwa a17 vcc gnd clk gw bwe oe adsc adsp adv sa sa dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc xq gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc nc sa sa sa sa sa sa sa 46 47 48 49 50 256k x 36 note:b a ll r5 connecting to v cc is acceptable note:pin 14 connecting to v cc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 7 ssr014-0b 08/13/2002 pin configuration 100-pin tqfp (t version) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a17 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwd synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce ,ce2, ce2 synchronous chip enable oe output enable dqa-dqd synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable dqpa-dqpd parity data i/o dqpb dqb8 dqb7 vccq gnd dqb6 dqb5 dqb4 dqb3 gnd vccq dqb2 dqb1 gnd scd vcc zz dqa8 dqa7 vccq gnd dqa6 dqa5 dqa4 dqa3 gnd vccq dqa2 dqa1 dqpa sa sa ce ce2 bwd bwc bwb bwa ce2 vcc gnd clk gw bwe oe adsc adsp adv sa sa dqpc dqc1 dqc2 vccq gnd dqc3 dqc4 dqc5 dqc6 gnd vccq dqc7 dqc8 nc vcc xq gnd dqd1 dqd2 vccq gnd dqd3 dqd4 dqd5 dqd6 gnd vccq dqd7 dqd8 dqpd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc sa sa sa sa sa sa sa sa 46 47 48 49 50 256k x 36 note:pin 14 connecting to vcc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d 8 integrated circuit solution inc. ssr014-0b 08/13/2002 pin configuration 119-pin pbga (top view) pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a18 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce , ce2 synchronous chip enable oe output enable dqa-dqb synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable dqpa-dqpb parity data i/o dqpa is parity for dqa1-8;dqpb is parity for dqb1-8 100-pin tqfp (d version) a b c d e f g h j k l m n p r t u vccq nc nc dqc1 nc vccq nc dqc4 vccq nc dqd6 vccq dqd8 nc nc nc vccq sa ce2 sa dqb2 nc dqc4 dqc3 nc vcc dqd5 nc dqd7 nc dqpd sa sa nc sa sa sa gnd gnd gnd bwb gnd nc gnd gnd gnd gnd gnd mode sa nc adsp adsc vcc xq ce oe adv gw vcc clk scd bwe a1 a0 vcc nc nc sa sa sa gnd gnd gnd gnd gnd nc gnd bwa gnd gnd gnd nc sa nc sa sa sa dqpa nc dqb7 nc dqb5 vcc nc dqa3 nc dqa2 nc sa sa nc vccq nc nc nc dqb8 vccq dqb6 nc vccq dqa4 nc vccq nc dqa1 nc zz vccq 1 2 3 4 5 6 7 sa nc nc vccq gnd nc dqpa dqa8 dqa7 gnd vccq dqa6 dqa5 gnd scd vcc zz dqa4 dqa3 vccq gnd dqa2 dqa1 nc nc gnd vccq nc nc nc sa sa ce ce2 nc nc bwb bwa a18 vcc gnd clk gw bwe oe adsc adsp adv sa sa nc nc nc vccq gnd nc nc dqb1 dqb2 gnd vccq dqb3 dqb4 nc vcc xq gnd dqb5 dqb6 vccq gnd dqb7 dqb8 dqpb nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc nc sa sa sa sa sa sa sa 46 47 48 49 50 512k x18 note:b a ll r5 connecting to v cc is acceptable note:pin 14 connecting to v cc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 9 ssr014-0b 08/13/2002 pin configuration pin descriptions a0, a1 synchronous address inputs. these pins must tied to the two lsbs of the address bus. a2-a18 synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synchronous controller address status adv synchronous burst address advance bwa - bwb synchronous byte write enable bwe synchronous byte write enable gw synchronous global write enable ce ,ce2, ce2 synchronous chip enable oe output enable dqa-dqb synchronous data input/output mode burst sequence mode selection scd single cycle deselect/dual cycle deselect mode control xq output drive control v cc +3.3v power supply gnd ground v ccq isolated output buffer supply : +3.3v or 2.5v zz snooze enable dqpa-dqpb parity data i/o dqpa is parity for dqa1-8;dqpb is parity for dqb1-8 512k x18 sa nc nc vccq gnd nc dqpa dqa8 dqa7 gnd vccq dqa6 dqa5 gnd scd vcc zz dqa4 dqa3 vccq gnd dqa2 dqa1 nc nc gnd vccq nc nc nc sa sa ce ce2 nc nc bwb bwa ce 2 vcc gnd clk gw bwe oe adsc adsp adv sa sa nc nc nc vccq gnd nc nc dqb1 dqb2 gnd vccq dqb3 dqb4 nc vcc xq gnd dqb5 dqb6 vccq gnd dqb7 dqb8 dqpb nc gnd vccq nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 mode sa sa sa sa a1 a0 nc nc gnd vcc nc sa sa sa sa sa sa sa sa 46 47 48 49 50 100-pin tqfp (t version) note:pin 14 connecting to vcc is acceptable
ic61s25632t/d ic61s25636t/d ic61s51218t/d 10 integrated circuit solution inc. ssr014-0b 08/13/2002 note: there are pull-up devices on the mode, xq, and scd pins and a pull down device on the zz pin, so those input pins can be unconn ected and the chip will operate in the default states as specified in the above table. truth table address operation used ce ce ce ce ce ce2 ce2 ce2 ce2 ce2 ce2 adsp adsp adsp adsp adsp adsc adsc adsc adsc adsc adv adv adv adv adv write write write write write oe oe oe oe oe dq deselected, power-down none h x x x l x x x high-z deselected, power-down none l x h l x x x x high-z deselected, power-down none l l x l x x x x high-z deselected, power-down none l x h h l x x x high-z deselected, power-down none l l x h l x x x high-z read cycle, begin burst external l h l l x x x x q read cycle, begin burst external l h l h l x read x q write cycle, begin burst external l h l h l x write x d read cycle, continue burst next x x x h h l read l q read cycle, continue burst next x x x h h l read h high-z read cycle, continue burst next h x x x h l read l q read cycle, continue burst next h x x x h l read h high-z write cycle, continue burst next x x x h h l write x d write cycle, continue burst next h x x x h l write x d read cycle, suspend burst current x x x h h h read l q read cycle, suspend burst current x x x h h h read h high-z read cycle, suspend burst current h x x x h h read l q read cycle, suspend burst current h x x x h h read h high-z write cycle, suspend burst current x x x h h h write x d write cycle, suspend burst current h x x x h h write x d partial truth table function gw gw gw gw gw bwe bwe bwe bwe bwe bwa bwa bwa bwa bwa bw bw bw bw bw b b b b b bwc bwc bwc bwc bwc bwd bwd bwd bwd bwd read h h x x x x read h l h h h h write byte 1 h l l h h h write all bytes h l l l l l write all bytes l x x x x x mode pin functions mode name pin name state function burst order control mode l linear burst h or nc interleaved burst power down control zz l or nc active h standby single / dual cycle deselect control scd l dual cycle deselect h or nc single cycle deselect output drive control xq l high drive (low impedance) h low drive (high impedance)
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 11 ssr014-0b 08/13/2002 interleaved burst address table (mode = vcc or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias ?40 to +85 c t stg storage temperature ?55 to +150 c p d power dissipation 1.6 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ?0.5 to v ccq + 0.5 v v in voltage relative to gnd for ?0.5 to v cc + 0.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd ?0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause perma-nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, p recautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. 0,0 1,0 0,1 a1', a0' = 1,1
ic61s25632t/d ic61s25636t/d ic61s51218t/d 12 integrated circuit solution inc. ssr014-0b 08/13/2002 dc electrical characteristics (over operating range) symbol parameter test con ditions min. max. unit v oh output high voltage i oh = ?2.0 ma, v ccq = 2.5v 1.7 ? v i oh = ?4.0 ma, v ccq = 3.3v 2.4 ? v v ol output low voltage i ol = 2.0 ma, v ccq = 2.5v ? 0.7 v i ol = 8.0 ma, vccq = 3.3v ? 0.4 v v ih input high voltage v ccq = 2.5v 1.7 v ccq + 0.3 v v ccq = 3.3v 2.0 v ccq + 0.3 v v il input low voltage v ccq = 2.5v ?0.3 0.7 v v ccq = 3.3v ?0.3 0.8 v i li input leakage current gnd v in v cc (1) ?2 2 a i lo output leakage current gnd v out v cc q, oe = v ih ?2 2 a notes: 1. the mode, zz, scd, xq, pin has an internal pullup. and input leakage = 10 a . power supply characteristics (over operating range) -250 -200 -166 -133 parameter test conditions symbol max. max. max. max. unit ac operating device selected, i c c 1 com. 3 9 0 3 6 0 3 3 0 3 0 0 m a supply current all inputs v il or v ih ind. 4 1 0 3 8 0 35 0 32 0 f = 1/t kc clock running device deselected, icc2 com. 110 100 90 85 ma v cc = max., ind. 130 120 110 105 ma all inputs v il or v ih f = 1/t kc coms standby device deselected, i sb com. 90 90 90 90 ma v cc = max., ind. 100 100 100 100 ma all inputs 0.2v or v cc -0.2v f = 0 power dowin mode v cc = max i zz com. 80 80 80 80 ma zz v cc - 0.2v ind. 90 90 90 90 ma f = 0 all input 0.2v or v cc -0.2v operating range range ambient temperature v cc v ccq commercial 0c to +70c 3.3v, +10%, ?5% 2.37 5? 3.6v industrial ?40c to +85c 3.3v, +10%, ?5% 2.37 5? 3.6v
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 13 ssr014-0b 08/13/2002 ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v for 3.3v i/o and reference level v cc q/2v for 2.5v i/o output load see figures 1 and 2 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: ta = 25c, f = 1 mhz, vcc = 3.3v. ac test loads figure 1 figure 2 output buffer z o = 50 ? 1.5v for 3,3v i/o v ccq /2v for 2.5v i/o 50 ? 317 ? /1667 ? 5 pf including jig and scope 351 ? /1538 ? output 3.3v for 3.3v i/o /2.5v for 2.5v i/o
ic61s25632t/d ic61s25636t/d ic61s51218t/d 14 integrated circuit solution inc. ssr014-0b 08/13/2002 read/write cycle switching characteristics (over operating range) -250 -200 -166 -133 symbol parameter min. max. min. max. min. max. min. max. unit t kc cycle time 4 ? 5 ? 6 ? 7.5 ? ns pipeline t kq clock access time ? 3 ? 3.1 ? 3.5 ? 4 ns t kqx (1) clock high to output invalid 1.0 ? 1.0 ? 1.5 ? 1.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? 0 ? ns t kh clock high pulse width 1.6 ? 2 ? 2.3 ? 2.8 ? ns t kl clock low pulse width 1.6 ? 2 ? 2.3 ? 2.8 ? ns t kqhz (1,2) clock high to output high-z ? 3.1 ? 3.1 ? 3.5 ? 4 ns t oeq output enable to output valid ? 3.1 ? 3.1 ? 3.5 ? 4 ns t oelz (1,2) output enable to output low-z 0?0? 0 ? 0?ns t oehz (1,2) output enable to output high-z ? 3.0 ? 3.0 ? 3.5 ? 4 ns t as address setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t ss address status setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t ws write setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t ces chip enable setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t avs address advance setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t ds data setup time 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns t dh data hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns t zz s zz setup time 2 ? 2 ? 2 ? 2 ? c y c t zz rec zz recovery time 2 ? 2 ? 2 ? 2 ? c y c note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 15 ssr014-0b 08/13/2002 pipelined scd read cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst 2a 2b
ic61s25632t/d ic61s25636t/d ic61s51218t/d 16 integrated circuit solution inc. ssr014-0b 08/13/2002 pipelined dcd read cycle timing single read high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw address adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 3b t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst 2a 2b
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 17 ssr014-0b 08/13/2002 write cycle timing single write data out data in oe ce2 ce2 ce bw4-bw1 bwe gw address adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce2 only sampled with adsp or adsc ce masks adsp unselected with ce2 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw4-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
ic61s25632t/d ic61s25636t/d ic61s51218t/d 18 integrated circuit solution inc. ssr014-0b 08/13/2002 read/write cycle timing: pipelined single read single write high-z high-z data out data in oe ce2 ce2 ce bw4-bw1 bwe gw addresses adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce1 inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2 and ce3 only sampled with adsp or adsc ce1 masks adsp unselected with ce3 t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t ds t dh t kqhz
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 19 ssr014-0b 08/13/2002 snooze and recovery cycle timing single read high-z high-z data out data in zz oe ce2 ce2 ce bw4-bw1 bwe gw address adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t zzs t zzrec
ic61s25632t/d ic61s25636t/d ic61s51218t/d 20 integrated circuit solution inc. ssr014-0b 08/13/2002 ordering information commercial range: 0c to +70c speed order part number package 250 mhz ic61s25632t-2 5 0tq 14*20*1.4mm lqfp ic61s25632d-2 5 0tq 14*20*1.4mm lqfp ic61s25632d-2 5 0b 14*22mm pbga 200 mhz ic61s25632t-200tq 14*20*1.4mm lqfp ic61s25632d-200tq 14*20*1.4mm lqfp ic61s25632d-200b 14*22mm pbga 166 mhz ic61s25632t-166tq 14x20x1.4mm lqfp ic61s25632d-166tq 14x20x1.4mm lqfp ic61s25632d-166b 14*22mm pbga 133 mhz ic61s25632t-133tq 14x20x1.4mm tqfp ic61s25632d-133tq 14x20x1.4mm tqfp ic61s25632d-133b 14*22mm pbga speed order part number package 250 mhz ic61s25636t-2 5 0tq 14*20*1.4mm lqfp ic61s25636d-2 5 0tq 14*20*1.4mm lqfp ic61s25636d-2 5 0b 14*22mm pbga 200 mhz ic61s25636t-200tq 14*20*1.4mm lqfp ic61s25636d-200tq 14*20*1.4mm lqfp ic61s25636d-200b 14*22mm pbga 166 mhz ic61s25636t-166tq 14x20x1.4mm lqfp ic61s25636d-166tq 14x20x1.4mm lqfp ic61s25636d-166b 14*22mm pbga 133 mhz ic61s25636t-133tq 14x20x1.4mm tqfp ic61s25636d-133tq 14x20x1.4mm tqfp ic61s25636d-133b 14*22mm pbga
ic61s25632t/d ic61s25636t/d ic61s51218t/d integrated circuit solution inc. 21 ssr014-0b 08/13/2002 speed order part number package 250 mhz ic61s51218t-2 5 0tq 14*20*1.4mm lqfp ic61s51218d-2 5 0tq 14*20*1.4mm lqfp ic61s51218d-2 5 0b 14*22mm pbga 200 mhz ic61s51218t-200tq 14*20*1.4mm lqfp ic61s51218d-200tq 14*20*1.4mm lqfp ic61s51218d-200b 14*22mm pbga 166 mhz ic61s51218t-166tq 14x20x1.4mm lqfp ic61s51218d-166tq 14x20x1.4mm lqfp ic61s51218d-166b 14*22mm pbga 133 mhz ic61s51218t-133tq 14x20x1.4mm tqfp ic61s51218d-133tq 14x20x1.4mm tqfp ic61s51218d-133b 14*22mm pbga industrial range: -40c to 85c speed order part number package 250 mhz ic61s25632t-2 5 0tqi 14*20*1.4mm lqfp ic61s25632d-2 5 0tqi 14*20*1.4mm lqfp ic61s25632d-2 5 0b 14*22mm pbga 200 mhz ic61s25632t-200tqi 14*20*1.4mm lqfp ic61s25632d-200tqi 14*20*1.4mm lqfp ic61s25632d-200b 14*22mm pbga 166 mhz ic61s25632t-166tqi 14x20x1.4mm lqfp ic61s25632d-166tqi 14x20x1.4mm lqfp ic61s25632d-166b 14*22mm pbga 133 mhz ic61s25632t-133tqi 14x20x1.4mm tqfp ic61s25632d-133tqi 14x20x1.4mm tqfp ic61s25632d-133b 14*22mm pbga
ic61s25632t/d ic61s25636t/d ic61s51218t/d 22 integrated circuit solution inc. ssr014-0b 08/13/2002 integrated circuit solution inc. headquarter: no.2, technology rd. v, science-based industrial park, hsin-chu, taiwan, r.o.c. tel: 886-3-5780333 fax: 886-3-5783000 branch office: 7f, no. 106, sec. 1, hsin-tai 5 th road, hsichih taipei county, taiwan, r.o.c. tel: 886-2-26962140 fax: 886-2-26962252 http://www.icsi.com.tw speed order part number package 250 mhz ic61s25636t-2 5 0tqi 14*20*1.4mm lqfp ic61s25636d-2 5 0tqi 14*20*1.4mm lqfp ic61s25636d-2 5 0b 14*22mm pbga 200 mhz ic61s25636t-200tqi 14*20*1.4mm lqfp ic61s25636d-200tqi 14*20*1.4mm lqfp ic61s25636d-200b 14*22mm pbga 166 mhz ic61s25636t-166tqi 14x20x1.4mm lqfp ic61s25636d-166tqi 14x20x1.4mm lqfp ic61s25636d-166b 14*22mm pbga 133 mhz IC61S25636T-133TQI 14x20x1.4mm tqfp ic61s25636d-133tqi 14x20x1.4mm tqfp ic61s25636d-133b 14*22mm pbga speed order part number package 250 mhz ic61s51218t-2 5 0tqi 14*20*1.4mm lqfp ic61s51218d-2 5 0tqi 14*20*1.4mm lqfp ic61s51218d-2 5 0b 14*22mm pbga 200 mhz ic61s51218t-200tqi 14*20*1.4mm lqfp ic61s51218d-200tqi 14*20*1.4mm lqfp ic61s51218d-200b 14*22mm pbga 166 mhz ic61s51218t-166tqi 14x20x1.4mm lqfp ic61s51218d-166tqi 14x20x1.4mm lqfp ic61s51218d-166b 14*22mm pbga 133 mhz ic61s51218t-133tqi 14x20x1.4mm tqfp ic61s51218d-133tqi 14x20x1.4mm tqfp ic61s51218d-133b 14*22mm pbga

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